Integrated Circuit Tpic6c596D of 8-Bit Shift Register IC

Prod Model:	TPIC6C596D
Number Of Elements:	1
Number Of Bits Per Element:	8
Voltage - Supply:	4.5 to 5.5 V
Operation Temperature:	-40 Degree C ~ 125 Degree C

Product Description

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Category	Integrated Circuits (ICs)
Family	Logic - Shift Registers
Manufacturer	Texas Instruments
Series	TPIC
Packaging	Tube
Part Status	Active
Logic Type	Shift Register
Output Type	Open Drain
Number of Elements	1
Number of Bits per Element	8
Function	Serial to Parallel, Serial
Voltage - Supply	4.5 V ~ 5.5 V
Operating Temperature	-40 degree C ~ 125 degree C
Mounting Type	Surface Mount
Package / Case	16-SOIC (0.154", 3.90mm Width)
Supplier Device Package	16-SOIC

 
Low rDS(on) ...7 Typ
Avalanche Energy ...30 mJ
Eight Power DMOS Transistor Outputs of
100-mA Continuous Current
250-mA Current Limit Capability
ESD Protection . . . 2500 V
Output Clamp Voltage . . . 33 V
Enhanced Cascading for Multiple Stages
All Registers Cleared With Single Input
Low Power Consumption
 
Description
The TPIC6C596 is a monolithic, medium-voltage,
low-current power 8-bit shift register designed for
use in systems that require relatively moderate
load power such as LEDs. The device contains a
built-in voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other low-current or
medium-voltage loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shift
register clock (SRCK) and the register clock
(RCK), respectively. The storage register trans-
fers data to the output buffer when shift register
clear (CLR) is high. When CLR is low, all registers
in the device are cleared. When output enable (G)
is held high, all data in the output buffers is held
low and all drain outputs are off. When G is held
low, data from the storage register is transparent to the output buffers. When data in the output buffers is low,
the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current
capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide
additional hold time for cascaded applications. This will provide improved performance for applications where
clock signals may be skewed, devices are not located near one another, or the system must tolerate
electromagnetic interference